In the manufacture of certain types of semiconductor integrated circuits, it is necessary to prepare dielectrically-isolated single-crystal silicon substrates or dielectrically-isolated single-crystal regions within the body of a silicon wafer. Various circuit elements, such as transistors, diodes, capacitors, resistors, etc. may be formed in the single-crystal silicon regions and interconnected with each other to form a monolithic integrated circuit.
One prior art process for the preparation of dielectrically-isolated single-crystal silicon regions is described in U.S. Pat. No. 4,017,341 issued to T. Suzuki et al. wherein a silicon single-crystal wafer is used as starting material. A desired pattern is then formed on the surface of the wafer and an insulating silicon oxide film (SiO.sub.2) is formed by a chemical vapor deposition method on the entire surface of the wafer. Next, a silicon polycrystalline layer is formed on the patterned surface of the wafer, i.e., on the SiO.sub.2 film. The opposite surface of the single-crystal wafer, i.e., the non-patterned surface of the wafer, is then lapped, etched or polished up to a desired level resulting in a plurality of single crystal island regions electrically isolated from one another and embedded in a silicon polycrystalline support with a SiO.sub.2 film interposed therebetween. The foregoing known process results in a dielectrically-isolated substrate exhibiting some curvature or warpage partially due to the difference in thermal coefficients between the single-crystal wafer and the polycrystalline layer. In other words, the thermal mismatch between the original wafer and the deposited polycrystalline silicon tends to warp the resulting structure. The latter cannot be uniformly polished in any subsequent polishing step resulting in an uneven contact between the polished single-crystal wafer and any photoresist mask required for the diffusion of various circuit elements of an integrated circuit.
Another known method of preparing dielectrically-isolated regions in a substrate which exhibits less curvature or warpage than a substrate formed in accordance with the above-described known process is disclosed in U.S. Pat. No. 4,079,506 issued to T. Suzuki et al. In such a known technique, a plurality of silicon single-crystal regions are supported by a laminated structure comprising an alternate stacking of silicon oxide films and silicon polycrystalline layers. A silicon oxide film is interposed between the single-crystal regions or islands and the multiple layer support structure for isolating the regions from one another as well as from the support structure. According to this known method, the formation of three to twelve silicon polycrystalline layers in the support structure can reduce bendings of the substrate resulting from the growth stress of the polycrystalline layers or from the difference in thermal expansion coefficients between the single crystal silicon and the polycrystalline layers. Although this known technique appears to solve the bending or warpage problem, the use of such an alternate multiple layer structure results in a delicate, time consuming, as well as expensive method for manufacturing isolated single-crystal regions. Moreover, the deposition of the polycrystalline layers takes place at high temperatures capable of deleteriously affecting the characteristics of the silicon-single crystal regions.